1. Field of the Invention
The present invention relates to an analog/digital (A/D) converter, and especially relates to a successive approximation type A/D converter and a conversion method thereof.
2. Description of Related Art
When low power consumption is demanded, a successive approximation type A/D converter is widely used for various types of control LSIs such as a microcomputer. In recent years, the demands of high speed operation and high accuracy increase for an A/D converter incorporated in a highly-developed and highly-functionalized system. Thus, realization of the high speed operation and the high accuracy operation is also demanded for the successive approximation type A/D converter widely used for the purpose of low power consumption.
FIG. 1 is a diagram schematically showing a successive approximation type A/D conversion method for obtaining 2 bits at each step. In this conversion method, the conversion can be performed to achieve a given resolution in a half of the number of times of conversion, compared to a successive approximation type A/D conversion method for obtaining 1 bit at each step, thereby being able to perform a high speed conversion. The successive approximation type A/D converter is generally configured by a sample and hold circuit, a comparator, a D/A converter, a logic circuit, and a timing generation circuit. In the conversion method shown in FIG. 1, the converter is configured to be able to attain 2-bit resolution in a single comparing operation by using a 2-bit internal A/D converter having three comparison levels.
The converting operation shown in FIG. 1 will be described. A case where an analog input voltage is 9.5/16 of a reference voltage (hereinafter, the reference voltage is referred to as Vref) is shown as an example in a 4-bit A/D converter. In a first comparison period, the three comparison levels are set to (12/16)Vref, (8/16)Vref, and (4/16)Vref, respectively. When a correct determination has been performed in the first comparison period, an output of the 2-bit internal A/D converter is “10” since (9.5/16)Vref of the analog input voltage is higher than (8/16)Vref and lower than (12/16)Vref. This “10” is set to bit 3 and bit 2 of a successive approximation register, and bits 1 and 0 of a successive approximation register are set to “01”, “10”, and “01”.
In a second comparison period, the three comparison levels are set to (11/16)Vref, (10/16)Vref, and (9/16)Vref, respectively. When a correct determination has been performed in the second comparison period, an output of the 2-bit internal A/D converter is “01” since (9.5/16)Vref of the analog input voltage is higher than (9/16)Vref and lower than (10/16)Vref. Since the result of “10” is obtained in the first comparison period and the result of “01” is obtained in the second comparison period, a final result of “1001” is obtained as the 4-bit A/D converter.
As shown in FIG. 1, in the successive approximation type A/D conversion method for obtaining 2 bits at each step, the number of times of the comparison to obtain a conversion result of N bits is no more than (N/2). However, when the determination is erroneous even once, the conversion result will be successively obtained in an incorrect search voltage range. In this case, the accuracy cannot be improved because a correct value cannot be obtained eventually. In the A/D conversion method in FIG. 1, a conversion speed is improved but there is a possibility of lowering conversion accuracy.
In “High Performance Successive Approximation ADC Architecture” (the Society for Electronic Circuit Study, ECT-06-31, Mar. 30, 2006) by Akira HAYAKAWA et al., an A/D converter is proposed in which the accuracy is improved by modifying the A/D conversion method in FIG. 1. FIG. 2 is a diagram for explaining an A/D conversion method in which even when determination has been incorrect at a former step of a comparing operation, a digital error correction can be performed at a latter step by performing the successive approximation conversion with redundancy. This A/D conversion method can be realized by using the 2-bit internal A/D converter having three comparison levels.
In a digital error compensation algorithm in the A/D conversion method of FIG. 2, when an output of the internal A/D converter in an nth comparison is “11”, “1” is added to a comparison result in a (n−1)th comparison and a comparison result in the nth comparison is set to “0”. In addition, when the output of the internal A/D converter in the nth comparison is “10”, a comparison result in the (n−1)th comparison is not changed and the comparison result in the nth comparison is set to “1”. Moreover, when the output of the internal A/D converter in the nth comparison is “01”, the comparison result in the (n−1)th comparison is not changed and the comparison result in the nth comparison is set to “0”. Furthermore, when the output of the internal A/D converter in the nth comparison is “00”, is added to the comparison result in the (n−1)th comparison and the comparison result in the nth comparison is set to “1”.
The above-mentioned converting operation will be described below by exemplifying a case where a 3-bit A/D converter whose analog input voltage is a reference voltage multiplied by 6.1/8. In a first comparison period, three comparison levels are set to (6/8)Vref, (4/8)Vref, and (2/8)Vref, respectively. When a determination indicates correct comparison in the first comparison period, an output of the internal A/D converter is “11”. In the second comparison period, the three comparison levels are set to (8/8)Vref, (7/8)Vref, and (6/8)Vref, respectively. When a determination indicates correct comparison in the second comparison period, an output of the internal A/D converter is “01”. By combining “11” and “01”, which are the outputs of the internal A/D converter in the first comparison period and the second comparison period, a 3-bit conversion result “110” is obtained. Specifically, when the output of the internal A/D converter in the second comparison period is “01”, the comparison result “01” in the second comparison period is treated as “0” without changing the comparison result “11” in the first comparison period.
Next, a case where the output of the internal A/D converter is “10” because of an erroneous determination in the first comparison period will be described. In the second comparison period, the three comparison levels are set to (6/8)Vref, (5/8)Vref, and (4/8)Vref, respectively. When a correct determination has been performed in the second comparison period, the output of the internal A/D converter is “11”. By combining “10” and “11”, which are the outputs of the internal A/D converter in the first comparison period and the second comparison period, a 3-bit conversion result “110” is obtained. Specifically, when the output of the internal A/D converter in the second comparison period is “11”, “1” is added to the comparison result “10” in the first comparison period and the comparison result in the second comparison period is treated as “0”.
In this manner, though the erroneous determination is made in the first comparison period, the conversion result “110” is same as when a correct determination is made. Since 2-bit resolution can be obtained in the first comparison period and 1-bit resolution can be obtained in second comparison period or later in the A/D conversion method in FIG. 2, the comparison of (N−1) times is only required to obtain a conversion result with N-bit resolution.
In case of the A/D conversion method shown in FIG. 2, even when an erroneous determination is made, the error can be correct in a subsequent comparing operation by providing a redundant search voltage range. Accordingly, an A/D converter can be highly-accurate. However, the number of times of the comparison increases because the comparison of (N−1) times is required to obtain a conversion result with N-bit resolution, resulting in difficulty realizing a high-speed conversion.